The exponential increase in the density of integrated circuits (ICs) predicted by Moore's law has been primarily driven by shrinking the dimensions of the individual semiconductor devices comprising these circuits. Smaller device dimensions reduce the size of circuits, and therefore lead to a reduction of overall die area (the actual area partitioned on a Si wafer corresponding to an individual integrated circuit), thus allowing for more transistors on a single die without negatively impacting the cost of manufacturing. However, getting more functions into each circuit generally leads to larger die size, which requires larger wafers.

Fig. 1 Growth of the density of microprocessors according to Moore's law. The vertical axis is numbers of transistors per chip.

The basic workhorse of the semiconductor industry over the past three decades is the Metal Oxide Semiconductor Field Effect Transistor or MOSFET. Its basic structure is comprised of two conducting regions (source and drain) separated by an insulating (oxide) gate over a channel, which can be turned on or off, a simple switch, and the basic building block for computer architectures based on two state logic. The critical length scale is the gate length, corresponding to the distance between the source and drain. As this length is reduced, all the corresponding dimensions of the device decrease in size or 'scale,' according to well defined scaling 'rules'. Besides reducing the area per transistor on the die, scaling down of the gate length reduces the time it takes to move charge (electrons) from the source to the drain, increasing the switching speed of the transistor and hence the clock speed that logic circuits operate. Successive generations of MOS transistor technologies are characterized in terms of this critical dimension, which for present state of the art commercial production, has already entered the nanometer (nm) scale dimension regime. Figure 2 shows scanning electron microscope photographs of Intel's current production transistors at the so-called 65 nm node, and successively shorter gate length devices realized in the research laboratory, down to 15 nm. Clearly, present day transistor technology is nanotechnology.

Fig. 2 Scaling of successive generations of MOSFETs into the nanoscale regime (from Intel, with permission).

As semiconductor feature sizes shrink into the nanometer scale regime, device behavior becomes increasingly problematic as new physical phenomena at short dimensions occur, and limitations in material properties are reached. Clearly, as we scale below 15 nm gate length, we eventually approach dimensions for which the channel just a few Si atoms long, at which point (or even much sooner), conventional MOSFET devices cannot scale further, and a saturation of Moore's law will occur. In fact, such a limit is already approaching in terms of the necessary Silicon Dioxide gate oxide thickness separating the gate metal from the channel, which for 25 nm gate length technology, must be thinner than 1 nm as predicted by the International Technology Roadmap of Semiconductors (ITRS)(1). Basically, this reduction in thickness is required in order to maintain acceptable drive current, and in order to maintain charge control of the channel, by locating the gate a close to the channel as possible as the lateral length sca. 1 nm is only a few atomic layers thick, and for such a thin dielectric, leakage currents through the gate degrade the performance and increase power dissipation. Industry is addressing this challenge by developing new dielectric materials with high permittivity, such that the effective gate capacitance is increased for a much thicker dielectric, giving better leakage performance.

Another issue leading to a saturation of Moore's law is manufacturability as dimensions become smaller. As a semiconductor device becomes smaller, its output characteristics are increasingly sensitive to manufacturing and material imperfections. For example, impurity atoms with a valence higher or lower than Si have to be introduced into the Si lattice at dilute concentrations in order to create free charges for carrying current, otherwise the Si would be insulating. This process is referred to as 'doping' the semiconductor, and in ultra-small devices, the random position of dopant atoms in the device may cause dramatic changes in the current-voltage characteristics from device to device in very small structures. While in a large device with many dopant atoms, this effect averages out, in very small structures, the potential landscape seen by electrons traversing the source to drain varys widely from device to device due to the particular location of the dopant atoms. Another source of device to device output characteristic variance is due to random variations in linewidths associated with lithography. Again, in very small devices, such process fluctuations may dominate the characteristics of a particular device. This sensitivity of nanoscale devices to process fluctuations means that not just manufacturing, but also circuit and architecture design techniques, must be developed to anticipate large device to device variations and even failures (fault-tolerant design).

In order to meet the challenges of shrinking gate lengths further into the nanometer scale regime, increasing device performance, and still maintaining control of charge in the channel with the gate, industry is moving away from the 'classic' planar, bulk Si MOSFET design used over the past two decades. In order to increase performance for a given gate length, there is an increased trend towards alternate materials grown in the active regions of the device, such as strained Si, alloys of Si and Ge, and even compound semiconductors. Such alternatives to bulk Si increase performance through superior transport properties, and hence faster switching. In order to maintain charge as gate lengths shrink, research and production device structures are presently becoming increasingly non-classical and three dimensional rather than planar, using Si on insulator technology (where a buried layer of oxide is introduced to isolate the device from the Si substrate), dual-gate and wrap around gates (in which the gate is above, below and around the sides of the channel, rather than simply on top), and nanowire shaped channels. Figure 3 illustrates one such technology, the so-called FinFET due to the fin-shaped gate. As can be seen, the structure is 3D in nature, where the channel resembles a 1D wire with nanometer scale dimensions (nanowire). This wire like nature of the channel becomes important in the consideration of future technologies based on self-organized 1D conductors such as Carbon Nanotubes (CNTs) and self-assembled semiconductor nanowires.

Figure 3 Non-Classical device structures. Left is a schematic of a FinFET, right is an SEM photo of a multileg FinFET structure.

Beyond these material and manufacturing issues, there are fundamental limits as device dimensions shrink. One is that quantum mechanics starts to play a role for small dimensions, in terms of the wave-like properties of charge carriers like electrons. Effects such as quantization of motion, interference effects, and tunneling are all physical effects which modify the performance of devices at small dimensions. Another is the discrete nature of charge. In small structures, charge can no longer be treated as a continuous fluid, rather the number of charges is finite and small, which can lead to so-called 'single electron charging' effects. For very small structures the change in energy and potential (voltage) due to one charge tunneling or otherwise moving from one conductor to another, gives rise to a noticeable fluctuation in voltage. This sensitivity is because the 'capacitance' (i.e. the proportionality between charge and voltage, Q=C V) is a geometrical quantity which reduces as the structure size shrinks. If C is sufficiently small (10^-17 F and less), then the change in voltage, V, for a single electron moving from one side to the other ( Q=1.6 10^-19C) may be larger than the thermal voltage, 25 mV at room temperature. All these effects can lead to noticeable degradation of the performance of classical and non-classical MOSFETS, eventually leading to the end of the roadmap for scaling. Beyond that, there has been extensive work over the past decade related to nanoelectronic or quantum scale devices, which actually utilize quantum mechanical and single electron effects, and operate on very different principles from conventional MOSFET devices. These alternatives may allow the continued scaling beyond the end of the current scaling roadmap, as discussed later.

As discussed earlier, as semiconductor device dimensions shrink to the nanoscale and beyond, the physics governing device behavior becomes complicated due to several factors. For large dimension devices, the picture of macroscopic current flow in a device is very analogous to fluid flow, in which charges and charge flow (current) appear continuous, and their motion described by the same classical hydrodynamic equations used in the field of fluid mechanics. As we shrink to small dimensions, its easy to see that at some level, charge is no longer continuous, that the motion of individual electrons becomes important in the behavior of nanoscale devices. On the one hand, this sensitivity to individual unwanted charges threatens the reliability and reproducibility of nanoscale CMOS devices. On the other hand, the ability to control the state of individual electrons, and correspondingly represent and store information, represents the ultimate limit of nanoscale device technology, which is the basis of so-called single-electron transistors and memories discussed later.

Another way in which the electronic behavior of small structures differs from macroscale systems is that electrons are governed by the laws of quantum mechanics, where matter exhibits both wave-like and particle-like behavior. One important length scale is so called De Broglie wavelength of an electron, which is the characteristic wavelength of matter waves in the quantum mechanics picture. The interaction of electrons with structures on this length scale resembles optics rather than classical dynamics, with effects such as diffraction, interference, quantization of motion and tunneling, all of which lead to marked changes from the classical fluid picture of charge transport. Such wave-like behavior can persist over long dimensions, depending on the so-called phase coherence length, i.e. the length over which an electron 'wave' remains coherent. Quantum computing is a new paradigm that explicitly depends on maintaining phase coherence, and utilizing the potential information stored in the phase of a quantum mechanical two-state system, to exponentially extend the processing power compared to a simple binary logic system based on the same two states. Coherence is destroyed by interaction of the electron with its energy dissipative environment, primarily the vibrational motion of the host material in inorganic and organic structures. Since this vibrational motion increases with increasing temperature and thereby reducing the coherence length, quantum mechanical effects tend to wash out at room temperature. Phase coherence lengths in Si for example at room temperature are only a few tens of nanometers.

Generally, in regards to the behavior of conventional Si MOSFETs, single charge and quantum mechanical effects adversely affect the performance, creating barriers to further scaling at some future limit which is rapidly being approached, as discussed earlier. Beyond field effect transistors, however, there have been numerous proposals and demonstrations of device functionality and circuits based on single electron and quantum mechanical effects. These include quantum interference, negative resistance, and single electron devices, realized in metals, semiconductors, nanowires, carbon nanotubes and molecular systems, as discussed in more detail below.

As dimensions become shorter than the phase-coherence length of electrons, the quantum mechanical wave nature of electrons becomes increasingly apparent, leading to phenomena such as interference, tunneling, and quantization of energy and momentum as discussed above. In fact, as was elegantly pointed out by IBM Physicist Rolf Landauer, for a one-dimensional conductor such as a nanowire, the system is very analogous to an electromagnetic waveguide with 'modes', each supporting a conductance less than or equal to a fundamental constant 2e²/h. Such quantization of conductance was first demonstrated at Cambridge University and Delft Univeristy in the late 1980s, in specially fabricated, split-gate field effect transistors at low temperatures, where the split-gate formed a one-dimensional channel in a field effect device. However, manifestations of quantized conductance appear in many transport phenomena such as universal conductance fluctuations, noise, and the quantum Hall effect. Many schemes were proposed for quantum interference devices based on analogies to passive microwave structures, such as directional couplers, and even coupled waveguides for quantum computing. Promising results have been obtained on ballistic Y-branch structures by the research group in Lund, Sweden, where nonlinear switching behavior and elementary logic functions have been demonstrated, even at room temperature.

Most attempts at realizing quantum coherent devices suffer from the same problems as scaling of conventional nanoscale MOSFETs, that of the difficulty in control of the desired waveguide behavior in the presence of unintentional disorder. This disorder can arise from the discrete impurity effects discussed earlier, as well as the difficulty for process control at true nanometer scale dimensions. A further fundamental limit to devices based on the quantum mechanical nature of matter at the nanoscale is the phase coherence length and phase coherence time for maintaining a quantum coherent state. As mentioned earlier, this time and length scale are typically quite short in Si at room temperature.

In recent years, scientists have been attempting to exploit another purely quantum mechanical aspect of charge particles for nanodevice applications, that of the electron spin. Spin refers to the intrinsic magnetic moment associated with elementary particles such as electrons, which can only manifest itself through measurement relative to some particular reference frame in one of two states, spin-up or spin-down. This 20th century discovery has no classical analogue, although the name itself implies an origin of magnetic moment due to a charge particle spinning around its own axis to generate a magnetic field. In terms of the practical manifestation of spin, the ferromagnetic behavior materials utilized in magnetic memory for example (a multi-billion dollar industry), is intrinsically associated with the interaction of spin states to form an ordered magnetic system. For nanoscale devices, the fact that there are two distinct states associated with spin has attracted researchers to the ability to encode information, either as simply binary information or as a prototypical 'qubit' for quantum information storage. One of the main advantages of controlling the quantum state of spin, is that spin is much more robust to preserving phase coherence compared to the ordinary quantum mechanical phase of an electron discussed earlier in connection with quantum interference type devices. Typical spin coherence times in semiconductors can be from nanoseconds up to milliseconds, which provides much more opportunity to realize quantum coherent devices for applications such as quantum computing.

Previously we mentioned the role of individual random charges as an undesirable element in the reproducibility of nanoscale FETs due to device to device variations. However, the discrete rather than continuous nature of charge of individual electrons at the nanolevel, and control of the motion of such electrons, is the basis of a great deal of research in single electron devices and circuits. The understanding of single electron behavior is most easily provided in terms of the capacitance, C, of a small tunnel junction (i.e. two small conductors separated by a very thin insulator). As mentioned earlier, capacitance is the proportionality constant relating the voltage difference between a pair of conductors to the net charge (positive on one, negative on the other) on the conductors (the simplest example being a parallel plate capacitor formed by two plates separated by an insulator). If a single electron tunnels across the thin junction from one side to the other, the change in net charge on the conductors results in a corresponding change in electrostatic energy, e2/C. When physical dimensions are sufficiently small, the capacitance (which is primarily a geometrical) is correspondingly small, so that the change in energy may be greater than the thermal energy, 3/2kT, resulting in the possibility of a 'Coulomb blockade', or suppression of conductance due to the necessity to overcome this electrostatic voltage barrier. This Coulomb blockade effect allows the experimental control of electrons to tunnel one by one across a junction in response to a separate control gate, which can be used to lower this voltage barrier. Figure 4 illustrates the operation of a so-called single electron transistor, consisting of two tunnel junctions connecting to a conducting 'island' or 'quantum dot', to which a second voltage source, Vg, is connected through a separate gate capacitor, Cg. As the gate voltage is increased, the Coulomb blockade is lifted when integer numbers of electrons tunnel through the structure, hence allowing control of electron motion one by one. Single electron transistors, turnstiles, pumps, elementary logic circuits and single electron memories have been demonstrated experimentally, functioning even up to room temperature. Room temperature operation is important for practical applications in not requiring special cooling or cryogenic technology, which would limit the applicability for e.g. portable electronics. As in the case of quantum interference devices, the technological difficulties arise from fluctuations due to random charges and other sources of manufacturing variation, as well as the difficulty in realizing lithographically defined structures with sufficiently small dimensions to have single electron charging energies larger than the thermal energy, 25 meV@300K.

Fig. 4 Schematic representation of a single electron transistor (SET) consisting of two tunnel junctions connecting a conducting 'island', biased by a drain-source voltage, and controlled by a gate voltage, Vg. Off resonance, electrons see a 'gap' in energy which prevents tunneling. Applying a voltage to the island through the gate allows electrons to tunnel one at a time, giving rise to a peak in conductivity.

There has been rapid progress in realizing functional nanoscale electronic devices based on self-assembled structures such as semiconductor nanowires (NWs) and carbon nanotubes (CNTs). Semiconductor nanowires have been studied over the past decade in terms of their transport properties, and for nano-device applications such as resonant tunneling diodes, single electron transistors, and field effect structures. Recently, there has been a dramatic increase in interest in NWs due to the demonstration of directed self-assembly of NWs via epitaxial growth. Figure 4 shows a scanning electron micrograph of such structures grown using vapor-liquid-solid epitaxy, where the dimensions of the nanowires are less than 10 nm. Such semiconductor NWs can be elemental (Si,Ge) or III-V semiconductors, where it has been demonstrated that such wires may be controllably doped during growth, and abrupt compositional changes forming high quality 1D heterojunctions can be achieved. Groups such as those at Harvard and Lund, Sweden, have demonstrated nanowire FETs, bipolar devices and complementary inverters synthesized using self-assembly. The ability to controllably fabricate heterostructure nanowires has led to demonstration of nanoelectronic devices such as resonant tunneling diodes and single electron transistors. The scalability of arrays of such nanowires to circuits and architectures has also begun to be addressed, although the primary difficulty is in the ability to grow and orient NWs with desired location and direction.

Fig. 5 Scanning electron micrograph of self-assembled Si nanowires grown by vapor-liquid-solid epitaxy (after T. Picraux et al.).

Carbon Nanotubes (CNTs) are currently the focus of considerable attention due to the many remarkable properties of this new structural state of carbon. Figure 6 shows a schematic of a CNT which is composed of Carbon atoms arranged in a stable tube configuration. It is a highly stable state of matter, very similar in concept to fullerenes like C60 (Buckyballs). The structure can be envisioned as a graphite sheet (where the Carbon atoms form hexagonal rings), which is rolled in a tube a few nanometers in diameter, as shown in Fig. 6a. In rolling the tube and joining itself, the Carbon rings forming the graphite structure can align in different offset configurations, characterized by their 'chirality'. Depending on the chirality, CNTs can be metallic, semiconducting, or insulating, all the components required in conventional semiconductor ICs technology (interconnects, transistors, and dielectrics). Field effect transistors have been fabricated from CNTs, and basic logic functions demonstrated by researchers at IBM and other research laboratories, as shown in Fig. 6b. The extreme sensitivity of the conductivity of the nanotube to an attached atom or molecule to the wall or tip of the nanotube, also makes CNTs very attractive as sensors, the subject of considerable research presently. The primary challenge faced today in the evolution of this technology is the directed growth of CNTs with the desired chirality, and positioning on a semiconductor surface, suitable for large scale manufacturing.

Figure 6 a) Different states of Carbon, including diamond, graphite, C60, and a carbon nanotube (right) (from Richard Smalley's image gallery, http://smalley.rice.edu/smalley.cfm)

Figure 6 b) Carbon nanotube inverter formed from p- and n-channel FETs (from IBM, with permission).

Perhaps the ultimate limit of size scaling are devices comprised of a small number of molecules, forming the basis of electronic systems realized with molecular devices, or molecular electronics (moltronics). Figure 7 below shows a schematic diagram of a nanoscale contact to a molecular device, through which current is passed. Here the molecular device is an organic chain, to which different side groups or molecules are attached to realize a desired functionality. The molecular chain structure shown below studied by Mark Reed (Yale) and James Tour (Rice) showed 'negative differential conductance (NDC)' in the current voltage characteristics, i.e. a decreasing current with increasing voltage. From a circuit standpoint, NDC appears as a negative resistance, which leads to signal amplification, and the possibility of bi-stable behavior since the circuit does not like to reside in the regime, which is the basis for elementary switching devices. Elementary molecular electronic architectures have been demonstrated by HP Research Laboratories using crossbar type logic.

A very attractive feature of molecular systems is the possibility of bottom up or self-assembly of functional systems. Such templated self-assembly is of course the basis of biological systems, which have exquisite complexity and functionality, as well as self-replication and self-repair. Such 'biomimetic' approaches to molecular circuits would represent an inexpensive alternative to the exponentially increasing cost of top down nanofabrication, which is currently driving fab costs into the billions of dollars. However, at present there is no clear cut manufacturing approach to self-assembly in the near term.

Figure 7 A molecular 'junction' (above), and the corresponding molecular device contacted by external leads.

Another difficulty in understanding and utilizing molecular electronic structures is separation of the intrinsic behavior of a molecular device, from the contacts themselves. In conventional devices, contacts are nearly ideal, providing a connection to the other devices and the external world through interconnects, and not affecting the intrinsic performance of devices except through well controlled parasitic contact resistances. As the number of devices per chip scales exponentially, the number of contacts and interconnects per device increases even faster, and from an architecture standpoint, system performance is increasingly dominated by the interconnects and not the devices themselves. In a nanoscale devices themselves, the contacts may in fact dominate the performance of the device, and at a minimum are an integral part of the device itself. This problem is particularly evident in molecular electronic devices, as the schematic of Fig. 7 indicates (where the contact is much larger than the device). This challenge remains one of the many issues to be solved in evolving molecular electronics as a future.

Notes:

1. International Technology Roadmap of Semiconductors, http://public.itrs.net/

Stephen M. Goodnick
Interim Deputy Dean of Engineering, Director of Nanoelectronics, Arizona State University
Delta Pi chapter — Oregon State University

A leading researcher in the emerging field of nanoelectronics, Dr. Goodnick also studies transport in semiconductor devices, computational electronics, and high-frequency and optical devices. He joined Arizona State in 1996 as chair of the Department of Electrical Engineering. Prior to that, he was a professor of electrical and computer engineering at Oregon State University. He is a past president of the Electrical and Computer Engineering Department Heads Association and a current member of the HKN Board of Governors. He was named a Fellow of the IEEE in 2004.